library ieee ;
use ieee.std_logic_1164.all;
use work.all;

-------------------------------------------------
entity cmp_dlatch is
port(	data_in:    in std_logic;
    	e:	        in std_logic;
    	data_out:   inout std_logic );
end cmp_dlatch;

-------------------------------------------------
architecture behv of cmp_dlatch is

    component cmp_not
        port( D_in:  in std_logic;
              D_out: out std_logic );
    end component;

    component cmp_and
    port( A: in std_logic;
          B: in std_logic;
          F: out std_logic );
    end component;

    component cmp_or
    port( A: in std_logic;
          B: in std_logic;
          F: out std_logic );
    end component;

    component cmp_buf
    port( D_in: in std_logic;
          D_out: out std_logic );
    end component;

    component cmp_nand
port(  	A:	in std_logic;
	B:	in std_logic;
	F:	out std_logic
);
end component;

 signal dyclkNo: std_logic;
  signal NoDYclokNO: std_logic;
 signal NoQ: std_logic;
 -- signal q: std_logic;
    
begin

   
    nand_o: cmp_nand port map (data_in,e,dyclkNo);
    nand_1: cmp_nand port map (dyclkNo, e,NoDYclokNO);
    nand_2: cmp_nand port map (data_out, NoDYclokNO,NoQ);
    nand_3: cmp_nand port map (NoQ, dyclkNo, data_out);
    -- buf_0: cmp_buf port map(q, data_out);


end behv;
